Three Roofline engineers to present at LLVM Developers’ Meeting 2026

Three Roofline software engineers will present at the 2026 US LLVM Developers’ Meeting, taking place 26–28 October in Santa Clara, California:

• Pooja Hemashekar will examine convolution performance on x86 and Arm CPUs using MLIR/IREE
• Luis Romero Rodriguez will share lessons from enabling the Qualcomm Hexagon NPU within IREE
• Ege Beysel will cover integrating RISC-V vendor extensions into MLIR-based compilers

The annual LLVM Developers’ Meeting brings together engineers and contributors working on LLVM, MLIR, Clang, and related open-source technologies to exchange technical knowledge, discuss engineering challenges, and share developments across the compiler ecosystem.

Roofline engineers’ talks at LLVM Developers Meeting 2026

Pooja Hemashekar: Improving convolution performance in MLIR/IREE

27 October 2026 | 11:30–12:00 PDT / 19:30–20:00 CET

Talk: Data-Tiled Convolution in MLIR/IREE: Approaching XNNPACK Performance, and the Limits of Structured Codegen

Pooja shows how data tiling can improve convolution performance in MLIR/IREE, and where structured code generation reaches its limits. Her approach compiles 2D convolution operations directly in data-tiled form, avoiding im2col, an intermediate data transformation commonly used to implement convolutions through matrix multiplication.

The performance findings differ across CPU architectures:

• x86 CPU: The implementation approaches the performance of XNNPACK, a library of highly optimized neural network operators, on a wide, out-of-order x86 core.

• Arm Cortex-A55 CPU: The data-tiling approach remains significantly slower than XNNPACK on an in-order Arm Cortex-A55 core.

Pooja investigates the performance gap using hardware performance counters, generated assembly, and code-generation experiments. Her presentation explores why efficient data layouts alone may not guarantee optimal performance and what additional microarchitecture-specific optimizations may be needed to close the gap.

Luis Romero Rodriguez: Retargeting an MLIR-based compiler to the Qualcomm Hexagon NPU

28 October 2026 | 11:00–11:30 PDT / 19:00–19:30 CET

Talk: From Generic to Hardware-Aware Pipelines: Lessons from Retargeting an MLIR-Based End-to-End Compiler to a New NPU

Luis shares lessons from Roofline's ongoing work on Qualcomm targets to bring up the Hexagon DSP/NPU within IREE.

His presentation follows the development process of adapting an MLIR-based end-to-end compiler to a new accelerator, starting from a CPU-based reference path and progressively introducing hardware-aware lowering.

Drawing on the Hexagon bring-up, Luis explores the systems design questions that arise when adapting existing compiler infrastructure to specialized hardware. Examples involving memory management, vectorization, and interactions between the compiler and runtime help illustrate some of the engineering decisions encountered during development.

The presentation shares practical experience from the Hexagon integration with other engineers working on MLIR-based compilers and hardware enablement.

Roofline's ongoing work is available in the IREE Hexagon plugins repository on GitHub.

Ege Beysel: Bringing RISC-V vendor extensions into MLIR-based compilers

28 October 2026 | 14:15–14:45 PDT / 22:15–22:45 CET

Talk: Bringing RISC-V Matrix and Vector Vendor Extensions into MLIR-based ML Compilers

Ege presents a practical approach to integrating vendor-specific RISC-V matrix and vector extensions into MLIR-based machine learning compilers. RISC-V vendors can introduce specialized instructions to accelerate machine learning workloads, but making those instructions available to compilers requires careful integration across MLIR and LLVM.

Using IREE as an open-source case study, Ege examines three approaches:

1. Existing MLIR dialects: Using abstractions such as linalg and vector to represent and lower machine learning computations. ‍
2. Target-specific MLIR dialects: Introducing representations for specialized hardware instructions where existing abstractions aren't sufficient. ‍‍
3. ‍LLVM intrinsics and inline assembly: Lowering directly to hardware-specific instructions where appropriate.

Drawing on ongoing RISC-V vendor-extension integration work in IREE, with examples from targets such as SpaceMiT and MIPS by GlobalFoundries, Ege compares the tradeoffs between development speed, maintainability, compiler optimization, and the ability to contribute changes upstream.

Sharing engineering experience with the LLVM community

The three presentations offer different perspectives on compiler development, from investigating performance limitations to working through the challenges of supporting new hardware.

• Pooja examines why data-tiled convolution approaches XNNPACK performance on x86 but remains significantly slower on Arm Cortex-A55, and what additional microarchitecture-specific optimizations may be needed.
• Luis shares the systems design questions and engineering decisions encountered while adapting an MLIR-based compiler to the Qualcomm Hexagon NPU, using examples from the bring-up process to illustrate the challenges.
• Ege compares techniques for integrating RISC-V vendor extensions, including the tradeoffs between development speed, maintainability, compiler optimization, and upstream contributions.

By presenting their work, Pooja, Luis, and Ege contribute technical findings and practical engineering experience to ongoing discussions within the LLVM and MLIR communities.

Attend the LLVM Developers’ Meeting 2026

The LLVM Developers’ Meeting takes place 26–28 October 2026 at the Santa Clara Marriott in Santa Clara, California.

If you're working on MLIR, IREE, or compiler support for new hardware architectures, join Pooja, Luis, and Ege in Santa Clara to hear about their latest engineering work, discuss technical challenges, and exchange ideas with the Roofline team.

View the full 2026 LLVM Developers’ Meeting program.

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