Today, Liquid AI released their new 230M parameter LLM. In their words, it's "the smallest model yet, built to run anywhere (CPUs, NPUs, and GPUs) to enable agentic applications on phones, robots, home and network automation devices.
"We are excited to showcase day-0 support with roofline's deployment tools.
Agentic home automation sounded exciting, so the demo below features a smart washing machine running a full multimodal workflow: LFM2.5-VL-450M provides visual intelligence, while LFM2.5-230M serves as the orchestration agent controlling the machine.
Both models are fully compiled and run on the CPU and eIQ® Neutron NPU on NXP Semiconductors' i.MX 95, demonstrating how new foundation models can instantly move from release to real-world edge deployments.Congrats to the Liquid AI team on the release!
#EdgeAI#AIDeployment#AICompiler#MLIR#IREE#Roofline#CoFundedByTheEU
MoE powers many of today's strongest LLMs. By activating only the experts each token actually needs, it packs far more performance into the same compute budget, a limited resource on the edge. But this only pays off if your deployment stack can handle the dynamic expert routing MoE depends on, and until now, edge AI compilers couldn't.
roofline closes this gap by bringing native MoE support to its IREE-based deployment stack.
In our latest case study, we compile and run MoE models end-to-end, from IBM's Granite 3.1 1B-A400M, through Liquid AI's LFM2-8B-A1B, up to Qwen-REAP-15B-A3B. The case study walks through the operators that were missing, how we enabled them, and includes a demo of the compiled models running end-to-end: https://lnkd.in/eqqtneKV
#EdgeAI#AIDeployment#AICompiler#MLIR#MoE#Roofline#CoFundedByTheEU
Our founders Jan Moritz Joseph and Dr. Thomas Zimmermann are excited to join EDGE AI FOUNDATION's Edge AI London 2026 on June 8 and 9, showcasing and discussing our latest progress.
🎤 Talk: In the talk 𝘈𝘭𝘪𝘨𝘯𝘪𝘯𝘨 𝘌𝘥𝘨𝘦 𝘈𝘐 𝘚𝘰𝘧𝘵𝘸𝘢𝘳𝘦 𝘢𝘯𝘥 𝘏𝘢𝘳𝘥𝘸𝘢𝘳𝘦 𝘐𝘯𝘯𝘰𝘷𝘢𝘵𝘪𝘰𝘯 𝘊𝘺𝘤𝘭𝘦𝘴 𝘵𝘩𝘳𝘰𝘶𝘨𝘩 𝘜𝘯𝘪𝘧𝘪𝘦𝘥 𝘚𝘰𝘧𝘵𝘸𝘢𝘳𝘦 𝘐𝘯𝘧𝘳𝘢𝘴𝘵𝘳𝘶𝘤𝘵𝘶𝘳𝘦, Jan Moritz Joseph will show how a unified open-source compiler and runtime ecosystem can close the gap between model and hardware innovation cycles, with real customer use cases on production SoCs. ⏱️ Mon, June 8th, 2:50 PM GMT+1 @ Mainstage
🗣️ Panel: Jan Moritz Joseph will also join the panel 𝘍𝘶𝘭𝘭 𝘚𝘵𝘢𝘤𝘬 𝘚𝘰𝘷𝘦𝘳𝘦𝘪𝘨𝘯𝘵𝘺 𝘪𝘯 𝘵𝘩𝘦 𝘈𝘨𝘦 𝘰𝘧 𝘗𝘩𝘺𝘴𝘪𝘤𝘢𝘭 𝘈𝘐 alongside NXP Semiconductors, Infineon Technologies, STMicroelectronics and Innatera to discuss what full stack sovereignty means for Europe's AI industry. ⏱️ Tue, June 9th, 11:00 AM GMT+1 @ Mainstage
📷 Demo: We are also bringing our latest demos, including Liquid AI's LFM2.5-350M running on NXP Semiconductors eIQ Neutron NPU and Toradex's Verdin iMX95, showing what it looks like to bring edge AI into production.
Come by our booth and say hi. We are around for the full conference!
#EdgeAI#AICompiler#MLIR#IREE#Roofline
Modern CPUs accelerate AI inference using SIMD (Single Instruction, Multiple Data) instructions. Arm’s Scalable Vector Extension (SVE) is a modern SIMD extension that introduces a vector-length-agnostic programming model, removing the assumption of a fixed vector length at compile time. However, this flexibility introduces substantial compiler challenges in vectorization, tiling, and data layout strategies.
Expanding on the earlier joint Arm x roofline case study on SVE support, this paper lays the groundwork for data layout strategies for scalable vector ISAs and evaluates these on ARM SVE.
1. We enabled data-tiled Arm SVE support in MLIR/IREE by making data layouts and tile sizes parametric in the hardware vector length, rather than fixed at compile time. This means a single compiled AI model runs efficiently across Arm CPUs with different vector lengths.
2. Our SVE code generation matches and often outperforms IREE's existing NEON code generation (up to 1.5× speedup), confirming that scalable data layouts do not regress performance despite the added compiler complexity. It also outperforms PyTorch ecosystem frameworks, with speedups of up to 1.7× over ExecuTorch and 6× over TorchInductor
3. In a cycle-level simulator study, our generated code scales with increasing SVE vector length, reaching up to 3.4× speedup when moving from 128-bit to 512-bit SVE on compute-bound workloads.
Great work by Ege Beysel, Maximilian Bartel, and Jan Moritz Joseph, and thanks to Andrzej Warzyński for the continuously great collaboration.
Read the full paper: https://lnkd.in/dTwt__ar
#MLIR #LLVM #AICompiler #EdgeAI #AIDeployment #Roofline
AI on the edge is moving fast—and that speed is both an opportunity and a problem. In this post, we introduce AI2EDGE, a publicly funded project supported by the European Union and the Ministerium für Wirtschaft, Industrie, Klimaschutz und Energie des Landes Nordrhein-Westfalen (MWIKE). The project brings together compiler technology and virtual platforms to make it easier to evaluate and deploy AI workloads on constrained, heterogeneous hardware. Before diving into the "how", it's worth clarifying the "why": edge AI deployment is still too hard, too slow, and too dependent on having the right hardware on your desk.
Training an AI model is only half the job. The other half — getting it to run reliably and efficiently on the target device — often consumes the most time. In practice, teams face a fragmented ecosystem: different frameworks and model formats (e.g., TensorFlow, Caffe, Apache TVM), rapidly changing toolchains, and inevitable incompatibilities. Some approaches age out quickly, leaving behind abandoned conversion scripts and brittle pipelines.
On edge devices (phones, embedded Linux systems, microcontrollers), the constraints are harsher: limited memory, limited compute, strict power budgets, and a smaller software stack. Even if you manage to get a model running, performance and efficiency can still be far from production-ready.
This is where the compiler toolchain of our partner Roofline AI comes into play: it helps bridge the gap between models and diverse hardware targets by turning AI workloads into efficient implementations for the chosen platform.
Compiler support alone doesn't remove a major real-world bottleneck: hardware availability.
Many companies evaluate multiple chips and acceleration options in parallel. But physical prototypes are often scarce, arrive late, or are shared among many teams. That makes early software bring-up, performance exploration, and regression testing difficult.
MachineWare addresses this with Virtual Platforms (VPs). A VP simulates a complete microprocessor-based system on a general-purpose computer. For example, a VP can include a RISC-V CPU model, peripherals, and a Neural Processing Unit (NPU):
When done well, software developers can work against a VP with the same workflows they would use on real hardware—often long before physical devices are broadly available. Because it's software, a VP can also be cloned, versioned, and integrated into CI/CD for repeatable regression testing.
Within AI2EDGE, MachineWare contributes their SIM-V instruction-set simulator for CPU simulation and their open-source peripheral modeling library VCML.
AI2EDGE combines these two worlds: Roofline's compilation technology and MachineWare's simulation technology. The goal is a workflow where teams can answer questions like: "Can my model run on chip X—and what performance should I expect?" …quickly and repeatedly, without needing physical prototypes. This enables rapid iteration across hardware options and reduces risk when selecting a target platform. Use cases and requirements are defined together with Fraunhofer IPT. Overall, the project aims to deliver an integrated system along the following lines:
If you're working on edge AI deployment and want to reduce the friction between "model trained" and "model running on target hardware," AI2EDGE is all about closing that gap—by pairing robust compilation with realistic, automation-friendly virtual platforms.
We are building the deployment platform for edge AI and are looking for exceptional people to join us.
If you want to help bring the next generation of AI software infrastructure to market, we would love to hear from you.
We have the following open positions:
- Content Marketing Lead
- AI Compiler Engineer (Senior Staff, Senior, Junior, Master Thesis)
- ML Infrastructure and Validation Engineer
- Build System & Packaging Engineer
All roles: https://lnkd.in/dA2y4f6y
#Hiring#EdgeAI#AIDeployment#AICompiler#Roofline
We're excited to present two talks at this year's EuroLLVM Developers' Meeting by the LLVM Foundation.
Florian Walbroel will present our open-source tool mlir-track-src for tracking operations through MLIR pass pipelines: https://lnkd.in/demfG--8
Ege Beysel will talk about optimizations for efficient tiling and vectorization in MLIR's linalg dialect.
Together with Maximilian Bartel, they will be in Dublin for the entire conference. Reach out if you are around!
#MLIR#LLVM#AICompiler#EdgeAI#AIDeployment#OpenSource#Roofline
